(1) Field of the Invention
The present invention relates in general to semiconductor devices and semiconductor manufacturing fabrication processes. More particularly, this invention presents an improved thermally robust semiconductor device having a metal electrode for both low power and high-performance sub-100 nm CMOS technologies.
(2) Description of the Prior Art
The whole of the semiconductor industry advancement is centered largely on the development of the device and processing techniques for its Complimentary Metal-Oxide-Semiconductor (CMOS) Field Effect Transistors (FET). In the very early days of MOSFET when aluminum was used as the metal gate, it only appears for a short period of time as the aluminum has a poor adhesion to the Silicon or Silicon di-oxide (SiO2) and high gate leakage so it was quickly replaced by poly-silicon with heavily doped N+ dopant. Polysilicon as a metal gate, or in short poly gate, has dominated CMOS technology for more than two decades. It has the advantages of good silicon adhesion, ease of processing, and no metal diffusion or penetration problems. Furthermore, the poly gate electrode can be readily scaled down without major impact to the CMOS processing. In high performance CMOS technology, when the gate size is scaled down to 0.15 and 0.13 um, dual doped gate electrodes (p+ dopant for the p-channel and n+ dopant for the n-channel) have been used to enhance its channel into surface mode. When CMOS devices are scaled further down to the sub-100 nm region, the gate oxide has shrunk to less than 5 nm, and the depletion layer formed in the polysilicon gate in inversion bias becomes a significant fraction of the gate capacitance and degrades the device performance. The use of a metal gate in these CMOS devices can alleviate this problem caused by polysilicon gate associated depletion effects and dopant penetration effects. See “International Technology Roadmap for Semiconductors”, Semiconductor Industry Association, San Jose, Calif., 2001 (ITRS-2001).
U.S. patent application Ser. No. 2003/0197230 suggests the use of two different metals with appropriate work functions: a first metal with a first work function for the PFET area and a second metal with a second work function for the NFET area. However, this approach adds significant cost and complexity to the process. Alternatively, the same metal can be used for the gate of both the PFET area and NFET area with a mid-gap work function. While refractory metal nitrides such as TaN and TiN have been extensively investigated as the potential solutions to replace poly-Si, these materials show limited thermal stability and thus are incompatible with conventional CMOS processes (with thermal processing for activating the source and drain regions). See “Physical and electrical properties of metal gate electrodes on HfO2 gate dielectrics,” by J. K. Schaeffer et. al., Journal of Vacuum Science and Technology Vol. 21(1), January/February 2003, p. 11-17 and “Thermal Stability of PVD TiN Gate and Its Impacts on Characteristic of CMOS Transistors,” by M. Wang et. al. 6th International Symposium on Plasma Process Induced Damage, May 14-15 Monterey Calif. USA, 2001, p. 36-39
The thermal stability of HfN is superior to TiN and TaN, due to its negatively larger heat of formation compared to that of TiN and TaN (HfN:-88.2, TiN:-80.4, TaN:-60.3; kcal/mol) See “Properties and microelectronic applications of thin films of refractory metal nitrides”, by M. Wittmer, Journal of Vacuum Science Technology A, vol. 3, pp. 1797-1803, 1985. An attempt making use of HfNx as the metal gate has been reported. Heuss et al. in his abstract (see Heuss at al. “Thermal stability of Hafnium and Hafnium Nitride (HfNx) Gate Electrodes on Silicon Dioxide”, Materials Research Society Proceedings, April 2000) discussed the use of HfNx as the metal gate material but do not recommend the application of HfN as the gate electrode. U.S. Pat. No. 6,225,168 to Gardner, et al. shows a metal gate electrode and a titanium or tantalum nitride as gate dielectric barrier layer and the processes for fabricating such devices. FIG. 1 shows a bulk CMOS with metal gate stack structure of Gardner et al. wherein TiN is the barrier metal and TaN is the capping layer.
U.S. Pat. No. 6,383,879 to Kizilyalli, et al. presents a method to form dual metal gates for the different work function for NMOS and PMOS transistors.
U.S. Pat. No. 6,511,911 to Besser, et al. gives a metal gate stack structure comprised of Tungsten, tantalum, TiN and etch stopper which is used for the deep submicron CMOS process. FIG. 2 depicts the gate stack structure of Besser et al. wherein tungsten is used as capping layer 18 and TiN as the barrier metal 14. Second metal layer Ta 16 is deposited in between the capping layer l8 and barrier layer 14.
U.S. Pat. No. 6,617,624 to Powell teaches a metal gate stack include a doped polysilicon, TiN and Tungsten with Nitride passivation and its formation processes
U.S. Pat. No. 6,043,157 to Gardner et al shows a process for forming dual gates where one gate is polysilicon and the other gate is metal.
U.S. Pat. No. 5,960,270 to Misra et al discloses a process wherein the same mid-gap work function metal is used for both n- and p-gates. U.S. Pat. No. 6,083,836 to Rodder teaches a dummy gate process where two gates are formed. For example, one gate is polysilicon and the other is aluminum. U.S. Pat. No. 6,051,487 to Gardner et al teaches a dummy gate process using a polysilicon or a metal gate.